# A Pipelined Multi-core MIPS Machine: Hardware Implementation by Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

By Mikhail Kovalev, Silvia M. Müller, Wolfgang J. Paul

This monograph is predicated at the 3rd author's lectures on laptop structure, given in the summertime semester 2013 at Saarland collage, Germany. It incorporates a gate point building of a multi-core computing device with pipelined MIPS processor cores and a sequentially constant shared memory.

The ebook comprises the 1st correctness proofs for either the gate point implementation of a multi-core processor and likewise of a cache established sequentially constant shared reminiscence. This opens how you can the formal verification of synthesizable for multi-core processors within the future.

Constructions are in a gate point version and hence deterministic. by contrast the reference versions opposed to which correctness is proven are nondeterministic. the advance of the extra equipment for those proofs and the correctness facts of the shared reminiscence on the gate point are the most technical contributions of this work.

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**Example text**

Eni (a)) . The following small example shows that this very formal and detailed set of rules captures our usual way of evaluating expressions: (x1 ∧ x2 )(0, 1) = x1 (0, 1) ∧ x2 (0, 1) = 0∧1 =0. Boolean equations, therefore, are written as e=e , where e and e are expressions involving variables x = x[1 : n]. They come in two ﬂavors: • Identities. An equation e = e is an identity iﬀ for any substitution of the variables a = a[1 : n] ∈ Bn , expressions e and e evaluate to the same value in B: ∀a ∈ Bn : e(a) = e (a) .

Hence, we get xt+1 = xt . An easy induction on t shows that ∀t ≥ 0 : xt = (t mod 2) . 2 The Detailed Hardware Model In the detailed hardware model, time is real-valued. Circuit signals y (which include register outputs) are functions y : R → {0, 1, Ω} where Ω stands for an either undeﬁned or metastable value. A circuit in the detailed hardware model is clocked by a clock signal ck which alternates between 0 and 1 in a regular fashion. When the clock signal switches from 0 to 1, we call this a clock edge.

6. Half adder Its inputs and outputs satisfy z= x s=0 y s=1. For multiplexers we use the symbol from Fig. 7(a). The n-bit multiplexer or short n-mux in Fig. 8(b) consists of n multiplexers with a common select signal s. Its inputs and outputs satisfy z[n − 1 : 0] = x[n − 1 : 0] s = 0 y[n − 1 : 0] s = 1 . For n-muxes we use the symbol from Fig. 8(a). Figure 9(a) shows the symbol for an n-bit inverter. Its inputs and outputs satisfy y[n − 1 : 0] = x[n − 1 : 0] . n-bit inverters are simply realized by n separate inverters as shown in Fig.