By Philip Teichmann
Adiabatic good judgment treats the full approach, overlaying all loss mechanisms and all circuitry had to construct adiabatic circuits, together with wiring and different parasitic parts. Readers also will research the applicability of ordinary layout automation instruments -- a tremendous trouble for clients.
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Extra info for Adiabatic Logic: Future Trend and System Level Perspective (Springer Series in Advanced Microelectronics) (Volume 34)
In Sect. 4 it is derived, that Adiabatic Logic gains less from voltage scaling. Thus decreasing the voltage supply will lead to a decreased ESF. 18 shows the impact of a reduced voltage on the energy dissipation of static CCNT as well as on ECRL and PFAL with (19, 0)-tubes. 2 Adiabatic Logic with Novel Devices 41 Fig. 17 The ESF gained by applying CNTFETs for ECRL Fig. 18 Impact of voltage scaling on the dissipation of a CNT-based inverter circuit CCNT circuit over the frequency). A quadratic dependence of the energy dissipation is observed for static CCNT and a linear reduction for Adiabatic Logic by scaling the voltage supply.
1 shows, that no distinct leakage behavior in CMOS and ECRL can be observed for the observed frequency regime. The losses of static CMOS are more or less constant over the whole simulated frequency range. 65 · Emin,P F AL ). In the adiabatic regime, PFAL dissipates less than the ECRL counterpart, due to the assisted charging via the logic blocks. At 100 MHz the energy dissipation of ECRL is approximately three times that of PFAL. Glancing at the ESF in Fig. 2 it is obvious, that PFAL is the Adiabatic Logic family of choice at the 65 nm node.
Though these facts are very convincing, a lot of barriers have to be overcome before MOSFETs made out of SWCNTs can be produced on a large scale. One limitation is the Shottky Barrier (SB) that is formed by any metalsemiconductor connection due to the different work functions . This limits the on-state current and thus the performance of the device. And additionally this leads to an ambipolar characteristic , the on-current is increased, when |VGS | is increased. In digital circuits, this leads to problems in transistor stacks, where negative gate-to-source voltages appear and thus turn on a device that has a “0” input .