Estonia - The Tallinn Experience

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From a register allocation viewpoint, this scheduling should be performed in such a way that value life times are minimized. Code compaction:. Local scheduling is frequently referred to as code compaction, if the target processor is a VLIW-like machine showing instruction level parallelism. 4), have already been generated, making code compaction typically a late compiler pass. Essentially the same techniques as for sequential scheduling can be used, but the scheduler is also responsible for exploiting the parallel functional units (FUs), so as to achieve the highest performance.

12 shows one of their results. Unfortunately, the authors do not provide many details about the retargetable compiler which they designed. 12. DSE with a compiler, considering interconnect 26 3. RETARGETABLE COMPILER TECHNOLOGY Design verification For architectures with heterogenous register files, it is not easy to always know the effect of deleting hardware resources during some optimization step. It can easily happen that the designer deletes too many resources. Compilation can be used to check if a certain hardware can actually perform a certain operation like a transfer between two specialized registers.

Output dependence: Vi and Vj write to the same storage resource R. Then, the schedule must preserve the original ordering of Vi and Vj imposed by the IR code. A scheduler assigns a start time t( v) to each node v E V. Generally, the goal is to construct a schedule with minimum total execution time. Any DG edge e = (Vi, Vj) has a weight w( e) that denotes the minimum start time difference between t(vj)- t(vi) in a valid schedule. Thus the DG edges, together with the available amount of processor resources, impose the constraints for the scheduler.

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