By Alexander Supalov, Andrey Semin, Christopher Dahnken, Michael Klemm
Optimizing HPC purposes with Intel® Cluster instruments takes the reader on a travel of the fast-growing region of excessive functionality computing and the optimization of hybrid courses. those courses quite often mix dispensed reminiscence and shared reminiscence programming versions and use the Message Passing Interface (MPI) and OpenMP for multi-threading to accomplish the final word target of excessive functionality at low strength intake on enterprise-class workstations and compute clusters.
The booklet makes a speciality of optimization for clusters which includes the Intel® Xeon processor, however the optimization methodologies additionally observe to the Intel® Xeon Phi™ coprocessor and heterogeneous clusters blending either architectures. in addition to the academic and reference content material, the authors deal with and refute many myths and misconceptions surrounding the subject. The textual content is augmented and enriched by way of descriptions of real-life situations.
What you’ll learn
- Practical, hands-on examples convey how you can make clusters and workstations in accordance with Intel® Xeon processors and Intel® Xeon Phi™ coprocessors "sing" in Linux environments
- How to grasp the synergy of Intel® Parallel Studio XE 2015 Cluster variation, inclusive of Intel® Composer XE, Intel® MPI Library, Intel® hint Analyzer and Collector, Intel® VTune™ Amplifier XE, and lots of different helpful tools
- How to accomplish speedy and tangible optimization effects whereas refining your realizing of software program layout principles
Who this ebook is for
software program pros will use this ebook to layout, increase, and optimize their parallel courses on Intel systems. scholars of machine technological know-how and engineering will worth the ebook as a complete reader, appropriate to many optimization classes provided world wide. The beginner reader will take pleasure in a radical grounding within the fascinating global of parallel computing.
Table of Contents
Foreword through Bronis de Supinski, CTO, Livermore Computing, LLNL
Chapter 1: No Time to learn this Book?
Chapter 2: evaluation of Platform Architectures
Chapter three: Top-Down software program Optimization
Chapter four: Addressing procedure Bottlenecks
Chapter five: Addressing software Bottlenecks: allotted Memory
Chapter 6: Addressing program Bottlenecks: Shared Memory
Chapter 7: Addressing program Bottlenecks: Microarchitecture
Chapter eight: software layout Considerations
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Extra info for Optimizing HPC Applications with Intel Cluster Tools: Hunting Petaflops
L. Hennessy and D. A. Patterson, Computer Architecture: A Quantitative Approach, 4th ed. (Burlington, MA: Morgan Kaufmann, 2006). 14. G. Hager and G. Wellein, Introduction to High Performance Computing for Scientists and Engineers (Boca Raton, FL: CRC Press, 2010). 15. D. A. Patterson, “Latency Lags Bandwith,” Communications of the ACM - Voting Systems, January 2004, pp. 71–75. 16. E. D. Lazowska, J. Zahorjan, G. S. Graham, and K. C. Sevcik, Quantitative System Performance: Computer System Analysis Using Queueing Network Models (Upper Saddle River, NJ: Prentice-Hall, 1984).
Application-level tuning is more complicated than system level because it requires a certain degree of understanding of algorithmic details. At the system level, we dealt with standard components—CPUs, OS, network cards, and so on. We rarely can change anything about them, but they need to be carefully chosen and correctly set up. At the 43 Chapter 3 ■ Top-Down Software Optimization application level, things change. Software is seldom made from standard components: most of its functionality is different from all other software.
In 2008, Intel announced doubling of the vector width to 256 bits in Intel AVX (Advanced Vector eXtensions) instruction set. The extended register was called ymm. The ymm registers can hold twice as much data as the SSE’s xmm registers. They support packed data types for modern x86 processor cores (for instance, in the fourth-generation Intel Core processors with microarchitecture, codenamed Haswell), as shown in Figure 2-8. 22 Chapter 2 ■ Overview of Platform Architectures Figure 2-8. AVX registers and supported packed data types The latest addition to Intel AVX, announced in 2013, includes definition of Intel Advanced Vector Extensions 512 (or AVX-512) instructions.