Defect and Fault Tolerance in VLSI Systems: Volume 2 by C. H. Stapper (auth.), C. H. Stapper, V. K. Jain, G. Saucier

By C. H. Stapper (auth.), C. H. Stapper, V. K. Jain, G. Saucier (eds.)

Higher circuit densities, a growing number of advanced software ohjectives, and complex packaging applied sciences have suhstantially elevated the necessity to contain defect-tolerance and fault-tolerance within the layout of VLSI and WSI structures. The objectives of defect-tolerance and fault-tolerance are yield enhancement and better reliahility. The emphasis in this quarter has ended in a brand new box of interdisciplinary clinical examine. I n truth, complicated tools of defect/fault keep an eye on and tolerance are leading to superior manufacturahility and productiveness of built-in circuit chips, VI.SI platforms, and wafer scale built-in circuits. In 1987, Dr. W. Moore equipped an "International Workshop on Designing for Yield" at Oxford collage. Edited papers of that workshop have been released in reference [II. The contributors in that workshop agreed that conferences of this sort may still he con­ tinued. preferahly on a every year hasis. It was once Dr. I. Koren who equipped the "IEEE Inter nationwide Workshop on illness and Fault Tolerance in VLSI structures" in Springfield Massachusetts the subsequent yr. chosen papers from that workshop have been puhlished because the first quantity of this sequence [21.

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4, pp. 230-234, December 1974. [100] J. Von Bank, "An Alternative Integrated Circuit Yield Model," IEEE Trans. on Reliability, vol. R-35, no. 4, p. 385-390, October 1986. [101] H. Walker, "Yield Simulation for Integrated Circuits", Kluwer Academic Publishers, Boston, 1987. [102] H. W. Director, "VLASIC: A Catastrophic Fault Yield Simulator for Integrated Circuits", IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, CAD 5(4), pp. 541556, 1986. [103] TJ. Wallmark, "Design Considerations for Integrated Electron Devices," Proc.

Ansley, "Computation of Integrated-Circuit Yield From the Distribution of Slice Yields for the Individual Devices," IEEE Trans. Electron Devices, Vol. ED-15, pp. 405-406, June 1968. [2] J. Bernard, "The IC Yield Problem: A Tentative Analysis for MOS/SOS Circuits," IEEE Trans. Electron Devices, vol. 939-944, Aug. 1978. [3] H. Bolouri and M. Lea, "ULSI and WSI Yield Estimation: An Empirical Approach" in Yield Modelling and Defect Tolerance in VLSI, (edited by W. Moore, W. Maiy, A. Strojwas), Adam Hilger, 1988.

O 200 A.. 0 800 1000 BLOC K SIZE Figure 4: Optimal redundancy as a function of block size. 6. ESTIMATING THE BLOCK SIZE As demonstrated in the previous sections, correct estimation of the block sir-e is essential for proper evaluation of the yield of circuits with redundancy. ermining the block size based on empirical data is not a standard statistical problem. Simple estimation based on averaging the si7;es of actual clusters is VNY dillicult since, given a defect mal>, it is not always clear what the boundaries of the clusters are.

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